Career Opportunities at the Boston-Area Office
To contact our Human Resources department, please e-mail careers@netronome.com.
The following opportunities are available in Boxborough, MA:
SoC Verification Engineer
Soc RTL Design Engineer
SoC Verification Engineer
JOB LOCATION – Boxborough, MA USA (Boston area)
DESCRIPTION
In this position, the successful candidate will be playing a key role in the logic verification of a high-performance network processor SoC, primarily testbench development (writing of stimulus generators, monitors/checkers, bus functional models, random test generation modules, simulation control, etc.), verification (test-plan development, test writing, simulation/debug, code/functional coverage) and automating steps, where applicable. The responsibilities may extend to executing gate-level simulation, as well. The successful candidate will be working closely with the architects, RTL design engineers and other verification engineers to ensure that the verification requirements are well-understood, coordinated and subsequently executed.
QUALIFICATIONS
Qualified candidates must possess a Bachelor’s degree in Electrical Engineering with 8-10 years of relevant experience or a Master’s degree in Electrical Engineering with 6-8 years of relevant experience.
MINIMUM REQUIREMENTS
- Very strong background in logic design, coding and verification
- Expertise in Verilog, SystemVerilog, Cadence NC-Verilog simulator, Perl scripting
- Expertise in development of verification components -- stimulus generators including random test generation, monitors/checkers, scoreboards, bus functional models, testbenches
- Expertise in coverage measurement and analysis using functional coverage, assertions and code coverage
- Experience with integrating third-party verification IP is a plus, as is familiarity with C/C++, and PCIe/DDR2-3/SPI4 protocols
- Experience doing gate-level simulation is also desirable
- Excellent problem-solving skills
- Good interpersonal skills
- Ability to quickly understand and define tasks to meet overall objectives and work independently with little supervision
- Good written and verbal communication skills with the ability to deliver high-quality output against deadlines are a must, as well as being able to work effectively in a cross-site team environment
SoC RTL Design Engineer
JOB LOCATION – Boxborough, MA USA (Boston area)
DESCRIPTION
In this position, the successful candidate will be playing a key role in the development of high-performance Network Processor SoCs. The successful candidate will be responsible for new RTL development, maintenance of existing RTL, and integration of externally developed IP blocks. In addition to delivering a bug-free design, the successful candidate will be responsible for achieving timing closure on their respective RTL Blocks. Working closely with the Architects, Validation, Physical, and Custom/Circuit design engineers to ensure that the requirements are well-understood, coordinated, and subsequently executed will also be required.
QUALIFICATIONS
Qualified candidates must possess a BSEE with 8-10 years of relevant experience or a MSEE with 6-8 years of relevant experience. Specific qualifications include:
- Very strong background in logic design, coding and verification including the development and maintenance of behavioral & structural RTL models
- Expertise in Verilog, Cadence NC-Verilog simulator & Perl scripting
- Proficiency in Timing Optimization & Timing Closure (Static Timing Analysis). Strong understanding of Cadence Synthesis tools a plus. This includes all aspects of post place & route timing closure challenges.
- Good interpersonal skills, be a quick learner, and ready to contribute wherever the need is
- Ability to quickly understand and define tasks to meet overall objectives and work independently with little supervision
- Good written and verbal communication skills and ability to deliver high-quality output against deadlines are a must, as well as ability to work effectively in a cross-site distributed team environment