Careers

The Netronome Silicon Engineering team is expanding, and thus presents a unique opportunity for qualified individuals to contribute to the success of the next generation of high performance NFP™ Network Flow Processors. These Data Processing Unit (DPU) devices are used in carrier-grade and enterprise-class communications products such as smartNICs that require deep packet inspection, flow analysis, content processing, virtualization, and security. Netronome is seeking highly motivated and experienced talented Design Verification Engineers to join the Silicon Engineering team to play a pivotal role in the creation of the next-generation high-performance devices which will be built on an advanced 7nm node.

• Definition and architecture of state-of-the-art, UVM-based, coverage-driven design verification environments
• “Hands-on” verification team leader for one or more major functional block(s)
• Day-to-day management and mentoring of members of the DV team, which may be geographically distributed
• Creation and execution of detailed verification test plans, including code development of new SystemVerilog components from bus functional models and test scripts
• Relentless management of “Bug Board” to prioritize and analyze defect trends (categorization, prioritization, aging, defect density etc.)
• Responsibility for the evidence based functional coverage and tapeout sign-off criteria

The ideal candidate would have ta solid combination of hardware, and software technical skills, as well as excellent communication skills (oral and written) including:

• Successfully leading a small team of engineers on tasks and technical practices while working well with geographically distributed teams and management.
• Extensive experience in coverage-driven design verification, networking protocols, system architecture and hardware design.
• A proven track record of successfully creating world-class DV environments that have delivered first-pass bug-free silicon.
• Expert-level understanding of OOP programming, pseudo-random verification techniques, and functional coverage.
• Experience with UVM/OVM SystemVerilog, Python, Verilog and Mercurial is highly desirable. Similar DV experiences with VMM SystemVerilog, C++, SystemC, Verilator, C, Perl, Clearcase/Perforce may also readily apply.  Specman eRM experience is viewed as a major plus.
• Proficiency with scripting languages (Perl, Python etc.)
• Ability to analyze system bottlenecks and characterize performance attributes.
• Experience verifying high-speed Ethernet with traffic management, PCIe, cryptography, microprocessors and complex cached memory subsystems is highly favored.
• Other desirable traits for select team roles may also include: packet switching SW, assembly/firmware microcoding (IXP, ARM), and post-silicon validation experience.
• Excellent problem solving and advanced debugging skills.
• Good interpersonal skills, ability to proactively and quickly learn new techniques plus a collegiate work style and willingness to contribute and support other team members,
• Self-motivated and able to work independently to achieve stretch goals in a timely manner
• Possess clear written and verbal communication skills, contributing directly to written plans and detailed technical specification
• Enthusiastically embrace the latest best practices in verification methodologies, techniques, and languages

Educational/Experience Requirements:
•    First Class honors bachelor’s degree (BSc) or and postgraduate degree, MSc or PhD, in Electrical/Computer Engineering or similar mathematical discipline
•    At least 10+ years of successful silicon hardware design experience for the senior roles
How to Apply:
Interested candidates should submit resumes to careers@netronome.com or click link below.

Netronome is recruiting highly motivated individuals to join its silicon design team.  In this position, you will play a key leadership role in the definition of the toolchain and development methodology to build Netronome’s fourth generation high-performance Network Flow Processors (NFP™), including responsibility for the back end detailed physical implementation.

Responsibilities:

The Lead Physical Design Engineer will have physical implementation responsibilities, including:

• Floor-planning, partitioning, P&R, timing reports, chip assembly, ECO process and final cleanup.
• Contributing to synthesis/APR methodology, timing constraints and block implementation.
• Working closely, and largely autonomously, with Architects and RTL Designers to ensure that requirements are well-understood, coordinated, and subsequently executed to deliver high quality silicon.

Requirements:

• Bachelor or Master’s Degree in Electrical Engineering or Computer Science degree or equivalent.
• PhD in a related discipline is also highly desirable
• 10+ years of relevant experience, including familiarity with the TSMC N7 process and libraries, and traditional back-end toolchain
• Experience with Full-chip Timing Closure, Constraint Generation, script configuration management and Timing Exceptions.
• Experience implementing complex Power-grids and clock tree design at the chip level. Additionally verifying the Signal Integrity correctness of these for EM/IR Drop.
• Experience in the chip assembly, DRC/LVS cleanup and GDSII generation for tapeout.
• Experience in partitioning and timing budgeting.
• Experience in block synthesis and APR.
• Solid understanding of hardware design fundamentals, computer and networking architecture and VLSI principles.
• Independent automation/parsing scripting experience in such languages as python/Perl/tcl is required. Programming experience in C++/java/other is a plus.
• Exposure to Verilog/VHDL coding and verification, CMOS circuits and digital design.
• Must be fundamentally a confident self-starter with excellent communications skills and a natural team player.
• Be able to quickly comprehend new challenges and be able to dissect and plan the discrete steps to successfully execute the back-end in a timely manner.
• Excellent written and verbal communication skills are desirable to work effectively with a geographically distributed development team.

Interested candidates should submit resumes to careers@netronome.com or click link below.

Netronome is seeking highly motivated experienced DFT Design and Verification Engineers to play a pivotal role in the implementation of a complex high-performance Network Processor SoC as part of its Silicon Engineering Team.
Responsibilities will focus in DFT implementation and design. Successful candidates will work closely with the System Architects and other design and verification engineers to ensure that requirements are well understood, coordinated, and subsequently implemented to the highest quality standards, measured by exhaustive coverage testing
The ideal candidate would have the right combination of technical and interpersonal skills including:

• Bachelor or Master’s degree in Electrical/Computer Engineering or equivalent
• PhD ns a related numerate or scientific discipline
• 15+ years of successful silicon hardware design experience
• Solid understanding of DFT hardware design fundamentals and VLSI principles, as well as expertise in Verilog/VHDL coding, CMOS circuits and digital design.
• A history of successfully delivering good hardware design with exhaustive coverage results
• A strong ability to conceive, document, and implement DFT processes and methodology in a considered, robust, and well-communicated documented manner
• Complete understanding of DFT (Design for Test) - Scan Insertion, ATPG and Test Pattern Compression, Memory BIST, Logic BIST, IEEE 1149.1 and 1149.6 JTAG & Boundary Scan
• Experience with tools such as Cadence’s Encounter, Modus and Mentor’s Tessent suite
• Experience with debug of DFT Rule Checking and Test Coverage methodology
• Experience with Test Pattern Generation, Verification, and minimization
• Experience with scripting languages (e.g., Perl, TCL, Python) and Makefiles
• Excellent critical thinking skills and aptitude for managing complexity
• Initiative-taking self-starter with first class communications skills required to work effectively with a distributed development team and third-party vendors including the foundry and test houses

How to Apply:
Interested candidates should submit resumes to careers@netronome.com or click link below.

This challenging position will be responsible for all technical aspects of Application Specific IC (ASIC) design implementation and integration including synthesis, floor-planning, clock and power distribution, global signal planning, I/O planning and hard-IP integration.
The successful candidate(s) will contribute to the logic verification, synthesis/APR and timing closure of RTL designs and will work closely with the System Architects and other RTL design and verification engineers to ensure that requirements are completely understood, documented, and subsequently implemented to the highest RTL standards of technical excellence and architectural correctness.

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or equivalent.
• A PhD in a related discipline is also highly desirable.
• 10+ years of successful silicon hardware design experience, ideally most recently with the TSMC N7 process or smaller geometry.
• Complete mastery of high-speed complex networking logic design and Verilog/VHDL design
• Experience working in a UNIX-like environment is typical.
• Experience with scripting (Perl, TCL, Python) and Makefiles is desirable.
• The successful candidate(s) will be self-starters with the ability and experience to contribute productively within a geographically distributed collegiate team
• Excellent communications skills (written and oral) to analyze and communicate status and to proactively recommend solutions to problems, as and when they arise
• Willingness to pursue aggressive challenging goals, without compromising technical correctness and the highest quality standards, buoyed by personal confidence, and proven technical ability

This challenging position will be responsible for all technical aspects of Application Specific IC (ASIC) design implementation and integration including synthesis, floor-planning, clock and power distribution, global signal planning, I/O planning and hard-IP integration.
The successful candidate(s) will contribute to the logic verification, synthesis/APR and timing closure of RTL designs and will work closely with the System Architects and other RTL design and verification engineers to ensure that requirements are completely understood, documented, and subsequently implemented to the highest RTL standards of technical excellence and architectural correctness.

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or equivalent.
• A PhD in a related discipline is also highly desirable.
• 10+ years of successful silicon hardware design experience, ideally most recently with the TSMC N7 process or smaller geometry.
• Complete mastery of high-speed complex networking logic design and Verilog/VHDL design
• Experience working in a UNIX-like environment is typical.
• Experience with scripting (Perl, TCL, Python) and Makefiles is desirable.
• The successful candidate(s) will be self-starters with the ability and experience to contribute productively within a geographically distributed collegiate team
• Excellent communications skills (written and oral) to analyze and communicate status and to proactively recommend solutions to problems, as and when they arise
• Willingness to pursue aggressive challenging goals, without compromising technical correctness and the highest quality standards, buoyed by personal confidence, and proven technical ability

The Netronome Silicon Engineering team is expanding, and thus presents a unique opportunity for qualified individuals to contribute to the success of the next generation of high performance NFP™ Network Flow Processors. These Data Processing Unit (DPU) devices are used in carrier-grade and enterprise-class communications products such as smartNICs that require deep packet inspection, flow analysis, content processing, virtualization, and security. Netronome is seeking highly motivated and experienced talented Design Verification Engineers to join the Silicon Engineering team to play a pivotal role in the creation of the next-generation high-performance devices which will be built on an advanced 7nm node.

• Definition and architecture of state-of-the-art, UVM-based, coverage-driven design verification environments
• “Hands-on” verification team leader for one or more major functional block(s)
• Day-to-day management and mentoring of members of the DV team, which may be geographically distributed
• Creation and execution of detailed verification test plans, including code development of new SystemVerilog components from bus functional models and test scripts
• Relentless management of “Bug Board” to prioritize and analyze defect trends (categorization, prioritization, aging, defect density etc.)
• Responsibility for the evidence based functional coverage and tapeout sign-off criteria

The ideal candidate would have ta solid combination of hardware, and software technical skills, as well as excellent communication skills (oral and written) including:

• Successfully leading a small team of engineers on tasks and technical practices while working well with geographically distributed teams and management.
• Extensive experience in coverage-driven design verification, networking protocols, system architecture and hardware design.
• A proven track record of successfully creating world-class DV environments that have delivered first-pass bug-free silicon.
• Expert-level understanding of OOP programming, pseudo-random verification techniques, and functional coverage.
• Experience with UVM/OVM SystemVerilog, Python, Verilog and Mercurial is highly desirable. Similar DV experiences with VMM SystemVerilog, C++, SystemC, Verilator, C, Perl, Clearcase/Perforce may also readily apply.  Specman eRM experience is viewed as a major plus.
• Proficiency with scripting languages (Perl, Python etc.)
• Ability to analyze system bottlenecks and characterize performance attributes.
• Experience verifying high-speed Ethernet with traffic management, PCIe, cryptography, microprocessors and complex cached memory subsystems is highly favored.
• Other desirable traits for select team roles may also include: packet switching SW, assembly/firmware microcoding (IXP, ARM), and post-silicon validation experience.
• Excellent problem solving and advanced debugging skills.
• Good interpersonal skills, ability to proactively and quickly learn new techniques plus a collegiate work style and willingness to contribute and support other team members,
• Self-motivated and able to work independently to achieve stretch goals in a timely manner
• Possess clear written and verbal communication skills, contributing directly to written plans and detailed technical specification
• Enthusiastically embrace the latest best practices in verification methodologies, techniques, and languages

Educational/Experience Requirements:
•    First Class honors bachelor’s degree (BSc) or and postgraduate degree, MSc or PhD, in Electrical/Computer Engineering or similar mathematical discipline
•    At least 10+ years of successful silicon hardware design experience for the senior roles
How to Apply:
Interested candidates should submit resumes to careers@netronome.com or click link below.

Netronome is recruiting highly motivated individuals to join its silicon design team.  In this position, you will play a key leadership role in the definition of the toolchain and development methodology to build Netronome’s fourth generation high-performance Network Flow Processors (NFP™), including responsibility for the back end detailed physical implementation.

Responsibilities:

The Lead Physical Design Engineer will have physical implementation responsibilities, including:

• Floor-planning, partitioning, P&R, timing reports, chip assembly, ECO process and final cleanup.
• Contributing to synthesis/APR methodology, timing constraints and block implementation.
• Working closely, and largely autonomously, with Architects and RTL Designers to ensure that requirements are well-understood, coordinated, and subsequently executed to deliver high quality silicon.

Requirements:

• Bachelor or Master’s Degree in Electrical Engineering or Computer Science degree or equivalent.
• PhD in a related discipline is also highly desirable
• 10+ years of relevant experience, including familiarity with the TSMC N7 process and libraries, and traditional back-end toolchain
• Experience with Full-chip Timing Closure, Constraint Generation, script configuration management and Timing Exceptions.
• Experience implementing complex Power-grids and clock tree design at the chip level. Additionally verifying the Signal Integrity correctness of these for EM/IR Drop.
• Experience in the chip assembly, DRC/LVS cleanup and GDSII generation for tapeout.
• Experience in partitioning and timing budgeting.
• Experience in block synthesis and APR.
• Solid understanding of hardware design fundamentals, computer and networking architecture and VLSI principles.
• Independent automation/parsing scripting experience in such languages as python/Perl/tcl is required. Programming experience in C++/java/other is a plus.
• Exposure to Verilog/VHDL coding and verification, CMOS circuits and digital design.
• Must be fundamentally a confident self-starter with excellent communications skills and a natural team player.
• Be able to quickly comprehend new challenges and be able to dissect and plan the discrete steps to successfully execute the back-end in a timely manner.
• Excellent written and verbal communication skills are desirable to work effectively with a geographically distributed development team.

Interested candidates should submit resumes to careers@netronome.com or click link below.

Netronome is seeking highly motivated experienced DFT Design and Verification Engineers to play a pivotal role in the implementation of a complex high-performance Network Processor SoC as part of its Silicon Engineering Team.
Responsibilities will focus in DFT implementation and design. Successful candidates will work closely with the System Architects and other design and verification engineers to ensure that requirements are well understood, coordinated, and subsequently implemented to the highest quality standards, measured by exhaustive coverage testing
The ideal candidate would have the right combination of technical and interpersonal skills including:

• Bachelor or Master’s degree in Electrical/Computer Engineering or equivalent
• PhD ns a related numerate or scientific discipline
• 15+ years of successful silicon hardware design experience
• Solid understanding of DFT hardware design fundamentals and VLSI principles, as well as expertise in Verilog/VHDL coding, CMOS circuits and digital design.
• A history of successfully delivering good hardware design with exhaustive coverage results
• A strong ability to conceive, document, and implement DFT processes and methodology in a considered, robust, and well-communicated documented manner
• Complete understanding of DFT (Design for Test) - Scan Insertion, ATPG and Test Pattern Compression, Memory BIST, Logic BIST, IEEE 1149.1 and 1149.6 JTAG & Boundary Scan
• Experience with tools such as Cadence’s Encounter, Modus and Mentor’s Tessent suite
• Experience with debug of DFT Rule Checking and Test Coverage methodology
• Experience with Test Pattern Generation, Verification, and minimization
• Experience with scripting languages (e.g., Perl, TCL, Python) and Makefiles
• Excellent critical thinking skills and aptitude for managing complexity
• Initiative-taking self-starter with first class communications skills required to work effectively with a distributed development team and third-party vendors including the foundry and test houses

How to Apply:
Interested candidates should submit resumes to careers@netronome.com or click link below.