The Netronome Silicon Engineering team is expanding, and thus presents a unique opportunity for qualified individuals to contribute to the success of the next generation of high performance NFP™ Network Flow Processors. These Data Processing Unit (DPU) devices are used in carrier-grade and enterprise-class communications products such as smartNICs that require deep packet inspection, flow analysis, content processing, virtualization, and security. Netronome is seeking highly motivated and experienced talented Design Verification Engineers to join the Silicon Engineering team to play a pivotal role in the creation of the next-generation high-performance devices which will be built on an advanced 7nm node.
The Director, Design Verification Engineering is a pivotal position, where the role is to initially recruit and build a team of first class DV Engineers. The Director will be responsible for developing the Design Verification methodology and specifically incorporating new solutions such as Cadence’s vManager ™ to automate large scale data-driven metric-driven verification across multiple sites and multiple projects. While the emphasis is on technical leadership, the individual may also serve as a Site Manager role.
Design Verification responsibilities will encompass the entire ASIC design verification process, including:
- Definition and architecture of state-of-the-art, UVM-based, coverage-driven design verification environments
- “Hands-on” verification team leader for one or more major functional block(s)
- Day-to-day management and mentoring of members of the DV team, which may be geographically distributed
- Creation and execution of detailed verification test plans, including code development of new SystemVerilog components from bus functional models and test scripts
- Relentless management of “Bug Board” to prioritize and analyze defect trends (categorization, prioritization, aging, defect density etc.)
- Responsibility for the evidence based functional coverage and tapeout sign-off criteria
The Director role requires a profound understanding of coverage-driven design verification fundamental techniques, microprocessor and/or networking architectures, expertise in SystemVerilog code development, as well as proven debug and bug diagnosis skills.
The successful candidate will lead a group of highly experienced design verification engineers in multiple locations, where technical knowledge is distributed via a strong collegiate ethos. The successful candidate will work closely with the system architects and RTL designers to ensure the highest-quality first-pass A0 silicon.
The ideal candidate would have ta solid combination of hardware, and software technical skills, as well as excellent communication skills (oral and written) including:
- Successfully leading a small team of engineers on tasks and technical practices while working well with geographically distributed teams and management.
- Extensive experience in coverage-driven design verification, networking protocols, system architecture and hardware design.
- A proven track record of successfully creating world-class DV environments that have delivered first-pass bug-free silicon.
- Expert-level understanding of OOP programming, pseudo-random verification techniques, and functional coverage.
- Experience with UVM/OVM SystemVerilog, Python, Verilog and Mercurial is highly desirable. Similar DV experiences with VMM SystemVerilog, C++, SystemC, Verilator, C, Perl, Clearcase/Perforce may also readily apply. Specman eRM experience is viewed as a major plus.
- Proficiency with scripting languages (Perl, Python etc.)
- Ability to analyze system bottlenecks and characterize performance attributes.
- Experience verifying high-speed Ethernet with traffic management, PCIe, cryptography, microprocessors and complex cached memory subsystems is highly favored.
- Other desirable traits for select team roles may also include: packet switching SW, assembly/firmware microcoding (IXP, ARM), and post-silicon validation experience.
- Excellent problem solving and advanced debugging skills.
- Good interpersonal skills, ability to proactively and quickly learn new techniques plus a collegiate work style and willingness to contribute and support other team members,
- Self-motivated and able to work independently to achieve stretch goals in a timely manner
- Possess clear written and verbal communication skills, contributing directly to written plans and detailed technical specification
- Enthusiastically embrace the latest best practices in verification methodologies, techniques, and languages
• First Class honors bachelor’s degree (BSc) or and postgraduate degree, MSc or PhD, in Electrical/Computer Engineering or similar mathematical discipline
• At least 10+ years of successful silicon hardware design experience for the senior roles
This position could be based in California and Massachusetts as well.
How to Apply:
Interested candidates should submit resumes to firstname.lastname@example.org or click link below.