Netronome is seeking highly motivated experienced DFT Design and Verification Engineer to play a pivotal role in the implementation of a complex high-performance Network Processor SoC as part of our Boxborough Silicon Engineering Team.
Responsibilities will focus in DFT implementation and design. Successful candidates will work closely with the system architects and other design and verification engineers to ensure that requirements are well understood, coordinated, and subsequently executed to deliver high quality silicon.
The ideal candidate would have the right combination of technical and interpersonal skills including:
- Bachelor or Master degree in Electrical/Computer Engineering or equivalent;
- 15+ years of silicon hardware design experience;
- Solid understanding of hardware design fundamentals and VLSI principles, as well as expertise in Verilog/VHDL coding, CMOS circuits and digital design;
- A history of successfully delivering good hardware design;
- A strong ability to devise, document, and implement processes and methods in a well-organized, robust, and well-communicated manner;
- Good understanding of DFT (Design for Test) - Scan Insertion, ATPG and Test Pattern Compression, Memory BIST, Logic BIST, IEEE 1149.1 and 1149.6 JTAG & Boundary Scan;
- Experience with Cadence Encounter Test;
- Experience with debug of DFT Rule Checking and Test Coverage Issues;
- Experience with Test Pattern Generation and verification;
- Experience with implementation and verification of JTAG, MBIST, LBIST, etc.;
- Experience with scripting (Perl, TCL, Python) and Makefiles;
- Excellent problem-solving skills;
- Good interpersonal skills, be a quick learner, and ready to contribute to a supportive team culture, wherever the need arises;
- Be able to quickly comprehend new challenges and plan the necessary tasks to meet overall objectives in a timely manner;
- Be self-motivated and able to work independently;
- Possess good written and verbal communication skills, being able to deliver high quality output against aggressive schedule.