CDNLive Cadence User Conference 2016
Aug 31, 2016 - 8:00 a.m. - 8:00 a.m. Burlington, MA
Netronome will have three presentations at CDNLive Boston 2016.
Ranjit LoboPrabhu, Senior Principal Design Engineer and Physical Design Technical Manager, will present "Chip Assembly and Signoff - The Need for an Integrated Design System" on August 31st from 10:30 a.m. - 11:10 a.m. ET.
Doug Duncan, Lead DFT Engineer, and Jarod Oatley, Silicon Design Engineer, will present "Domain Blocking Logic Insertion and Verification" on August 31st from 3:25 p.m - 4:05 p.m ET.
Salma Mirza, Lead Silicon Design Engineer, will present "Accelerating 22nm Design Verification in Pre-Silicon Environment with Production Software" on August 31st from 4:10 p.m. - 4:50 p.m. ET.