OCP Regional Summit
Sep 26, 2019 - Sep 27, 2019 - Amsterdam RAI Exhibition and Convention Centre, Amsterdam, NL
Netronome will be present several sessions at this OCP Regional Summit. Join our experts as they discuss, “Increasing network throughput and reducing CPU utilization by offloading KTLS onto crypto-capable SmartNIC – a case study,” and “Leveraging OCP Yosemite v2 servers to build a more cost efficient and performant AI Inferencing architecture.” Additionally, the OCP ODSA Project Group will present a half-day workshop with the following sessions at this OCP Regional Summit: "Motivation for ODSA/Fit into OCP," by Dharmesh Jani of Facebook The ODSA is a new and exciting project under the OCP Server subgroup. With the decline of Dennard’s scaling and evident slow down to crawl of Moore’s Law, a new approach is needed within industry to continue developing cost effective solutions for AI/ML/Networking use cases which take advantage of existing developments in the standard areas such as I/O interfaces while allowing for innovations in specific areas such as accelerators. ODSA enable this approach for a continued innovation. OCP is the de-facto open source hardware initiative for data center and infrastructure, and now with ODSA being a part of OCP, we can expect exciting fast solutions at system level center around ODSA-based modules. In this talk, we will look at some analogous use cases such as OAM and how similar approach can be leveraged by the industry to promote and enable ODSA engagement and adoption among developers and users alike. "The Open Domain-Specific Architecture: A Technical Introduction," by Bapi Vinnakota of Netronome The Open Domain-Specific Architecture aims to develop an open architectural interface to support chiplet-based design for domain-specific architectures. Domain-specific architectures are programmable high-performance products designed to execute high-intensity workloads, such as machine learning, networking and storage, efficiently. Chiplet-based designs implement integrated products by partitioning a design across multiple die instead of a single monolithic design. The ODSA aims to define an open interface such that chiplets from multiple vendors that support the interface can be assembled into domain-specific products. The ODSA started as an informal industry working group in November, 2018 and became an OCP sub-project in March, 2019.This talk will introduce the audience to the ODSA and its three workstreams: (a) Interface Definition; (b) Business and workflow; (c) Reference implementations. The talk will review recent results developed by the group and their relevance and significance to the technical goals of the group. The talk will highlight a new analysis of PHY interconnect technologies and design process learned from the PoC. Talks in the session by other speakers will cover technical results in each workstream in greater detail. The talk will also cover areas where the ODSA group is looking for assistance from new participants. "Bunch of Wires Interface," by Ramin.Farjad of Aquantia Multi-Chiplet system-in-package designs have recently received a lot of attention as a mechanism to combat high SoC design costs and to economically manufacture large ASICs. Multi-Chiplet designs require low-power area-efficient inter-Chiplet communication. Current technologies either extend on-chip high-wire count buses using silicon interposers or off-package serial buses over organic substrates. The former approach leads to expensive packaging. The latter usually too complex to design. In this paper, we propose a simple Bunch of Wires (BoW) interface that operates in three modes, Base, Fast and Turbo. This interface combines the ease of development of parallel interfaces with the low cost of organic substrates, while providing throughput efficiencies up to 1Tbps/mm and a power efficiency below 0.7pJ/bit. "Accelerating Innovation Through Chiplets and the Advanced Interface Bus (AIB)," by David Kehlet of Intel Chiplets, in particular silicon die interconnected and copackaged, have become mainstream in Systems-on-a-Chip (SoCs) from Intel, AMD and others, enabled by advanced packaging technologies. Chiplets provide an advantageous means to introduce new I/O and computation capabilities to SoCs, by avoiding a monolithic silicon redesign of the SoC. Broader adoption of chiplets into lower cost or lower volume products can be enabled by reducing the time and expense of die-to-die interface development and expanding access to advanced packaging technologies. Standardization to achieve chiplet interoperability is possible within technical and business bounds. In this presentation we will examine how the high density of advanced packaging technologies has enabled the wide parallel bus as a high bandwidth, lower power die-to-die interface. Wide parallel busses of 1,000 or more wires between die that are co-packaged using an advanced packaging technology can provide lower development cost, lower unit cost, lower latency and lower power than other interfaces. The Advanced Interface Bus (AIB) is an open wide parallel interface PHY standard for die-to-die communications. With the AIB logic design open sourced in early 2019, and development in progress on open source enablement of AIB physical design, development effort and expense for die-to-die interfacing is intended to drop dramatically. Interoperability is a key goal of an ecosystem of chiplets. At the PHY level (the electrical, signaling and mechanical interface), business and technical considerations will likely keep a plurality of PHY options. A variety of die-to-die PHYs is likely to continue forward in the same way that PCI Express, Ethernet and DDR coexist in a system. Still, interoperability at another level such as the link layer protocol is possible. In this presentation we will examine useful protocols between chiplets and recommend protocol interoperability paths forward. "The Chiplet Design Exchange," by Jawad Nasrullah of zGlue Machine-readable chiplet data exchange is the key for design automation, especially for modular designs. Chiplet's need to be described in terms of their physical and electrical characteristics at the very least but more importantly the key architectural description can help with design planning. There are business challenges for smooth data sharing, IP protection, and information control and a standard will help in the creation of the ecosystem. Based on zGlue Chiplet Exchange Format (ZEF), we are surveying and specifying standard practices and formats of Chiplet Data Exchange (CDX). "ODSA PoC," by Quinn Jacobson of Achronix Developing a proof-of-concept (PoC) for an emerging technology is important to learn what can and cannot be easily done, to reduce risk for future implementations, and lastly to convince skeptics that the technology is viable. This is true for the Open Domain-Specific Architecture (ODSA) effort where our PoC effort is trying to simultaneously address three dimensions of standardizing chiplet development. First, we need to address architectural issues like validating interface protocols, evaluating performance trade-offs, and developing software programming models. Second, we need to explore physical challenges like packaging issues, power distribution limitations, and high-speed I/O interfaces. Third, we need to expose the business issues that are unique to chiplets like how to share highly sensitive information on silicon design and business metrics that are exposed at the bare die-level. For the ODSA PoC workstream we have chosen to implement a module that can serve as a Smart Network Interface Card and also potentially as a Computation Storage Solution. This is an area where people are likely to create future domain-specific accelerators and represents a problem hard enough to expose real-world issues. It is also an area where members of the ODSA community have expertise and existing silicon components that can be leverage for creating a PoC. The physical implementation of the PoC involves a package design and a software development board created with discrete components. The PoC workstream focuses on a) architecture, b) physical implementation of package and board, c) bring up and testing. The board is architected in a modular manner such that the board design effort directly translates to the substrate design. "The Impact of Domain Specific Acceleration and Chiplet Technology on the Semiconductor and Electronics Business," by Sam Fuller of NXP As we reach the end of Moore’s Law, the semiconductor industry is looking for new ways to continue to deliver ever increasing processing capabilities to customers. Domain specific acceleration and chiplet technology are complementary technologies that show a lot of promise in this regard. This session will review the technical and business challenges that the microelectronics industry currently faces and how the ODSA workgroup is working to solve them. It will also review the new business models that must emerge to support this new advancement in microelectronics.