RISC-V Summit

RISC-V Summit

Dec 3, 2018 - Dec 6, 2018 - Santa Clara Convention Center, Santa Clara, CA

Join Netronome December 3 - 6 at the RISC-V Summit in booth 407. Netronome will also be holding two sessions at the summit:

Massively Parallel RISC-V Processing with Transactional Memory

Tuesday, December 4, 2018 - 2:40pm - 3:00pm

Steve Zagorianakos, Distinguished Engineer

In this talk, we discuss some of the background, and describe the example of a thousand RISC-V harts performing the processing required in a SmartNIC. We show how a RISC-V solution can be tailored with a suitable choice of instruction set features, privilege modes and debug methodology. Learn more.

Command-Driven Data Transfer Protocols in RISC-V SoCs

Wednesday, December 5, 2018 - 3:30pm - 3:50pm

Gavin Stark, Chief Scientist

In this talk, we propose that high-performance multi-core systems with hundreds of cores may also need a third kind of data management protocol: programmer-managed bulk- and atomic-data transfers. The talk will demonstrate how workloads can benefit from such a protocol. Learn more.

Register Here