RISC-V Summit

Dec 3, 2018 - Dec 6, 2018 - Santa Clara Convention Center, Santa Clara, CA

Netronome held two sessions at the RISC-V summit, Massively Parallel RISC-V Processing with Transactional Memory and Command-Driven Data Transfer Protocols in RISC-V SoCs on December 4 and 5

Massively Parallel RISC-V Processing with Transactional Memory
Steve Zagorianakos, Distinguished Engineer

In this talk, we discuss some of the background, and describe the example of a thousand RISC-V harts performing the processing required in a SmartNIC. We show how a RISC-V solution can be tailored with a suitable choice of instruction set features, privilege modes and debug methodology. View Slides.

Command-Driven Data Transfer Protocols in RISC-V SoCs
Rajesh Vaidheeswarran, Director of Engineering

In this talk, we propose that high-performance multi-core systems with hundreds of cores may also need a third kind of data management protocol: programmer-managed bulk- and atomic-data transfers. The talk will demonstrate how workloads can benefit from such a protocol. View Slides.