Composable Silicon IP Blocks

The increasing rate of change in protocols and algorithms related to networking, security and machine learning, coupled with the slowing down of Moore’s Law has prompted growing interest in heterogeneous processing and flexible coprocessor-based SoC designs. While coprocessors offload and accelerate specific workloads, data movement efficiency across the processing cores and memory in such SoC designs is becoming paramount. New server designs with heterogeneous processing change the paradigm of IP to SoC development where traditional IP design blocks are no longer adequate. The new world of efficient coprocessor designs requires more proven, complete and composable IP blocks in all areas – network and host interfaces, internal and external memory, hardware accelerators and processing logic – working together to enable the most efficient data movement.