Netronome is founded by Niel Viljoen, David Wells and Johann Tönsing with the idea to develop programmable flow co-processing solutions that accelerate network and security processing in x86-based servers, virtualized and non virtualized.
Releases its first generation of 4x1GbE SmartNICs based on Intel IXP28XX NPU and FPGA technologies. Also, releases the industry’s first software-defined solution based on the Netronome Flow Manager (NFM).
Licenses IXP NPU micro engine (ME) processor technology and associated software from Intel Corporation. Licenses ARM processor technology from ARM Holdings. Integrates them with Netronome’s PCIe technology to develop the network flow processor (NFP).
Establishes itself as a fabless semiconductor company with a dedicated silicon development team in Boxborough, Massachusetts.
Launches the NFP-3K line of networking co-processors, and enhances performance by adding 10GbE and PCIe Gen2 support. Fundamentally changes the silicon architecture to enable easier programming using Run-to-Completion (RTC) model for programming networking datapaths.
Based on the NFP-3K, introduces the second generation of 10GbE SmartNICs for accelerating x86-based servers and appliances. Delivers turnkey software for security and networking applications.
Evolves the Netronome software solutions to include standards-based flow and SDN frameworks using OpenFlow and Open vSwitch (OVS).
Sells its SSL inspection application software technology to Blue Coat Systems, while retaining all of its silicon and core software intellectual property. Establishes OEM customer relationship with Blue Coat supplying SmartNICs and associated software.
Introduces its third generation of 10/40/100GbE flow processing SmartNICs based on the NFP-6K, delivering enhanced turnkey Open vSwitch (OVS) and OpenFlow-based SDN gateway and security software applications, designed for x86-based network appliances.
Launches the NFP-6K flow processors. Makes fundamental improvements in the NFP silicon architecture: adds 40GbE and 100GbE ports, 5X more processing cores, a distributed mesh switching fabric, multiple integrated PCIe Gen3 interfaces, increased multi-threading performance between processing, accelerator and memory elements in the silicon, and DRAM-based wild-card matching capability.
Demonstrates P4 and C based programming on its SmartNICs, allowing users to change the behavior of networking hardware in cloud-based SDN and NFV deployments at the speed at which one can change open source networking software in servers.
Releases the industry’s first P4 and C Integrated Development Environment (IDE) to enable simple and vendor-agnostic datapath programming on the generally available SmartNICs.
Introduces its fourth generation of 10/40GbE SmartNICs, branded as SmartNICs, using the new NFP-4K and production ready Agilio OVS software. Announces roadmap to support 25GbE, Contrail vRouter and Linux Firewall during the course of the year.